======================FLIP_FLOP======================================= MASTER-SLAVE D FLIP-FLOP _______ ____| D Q |__ | | __/\|>CLK /Q|__ \/|_______| _______ _______ _______ CLK__| |________| |________| |___ _______ ________________ D0 ______| |__________________| _________________ ____ Q __________| |________________| ____ _______\ \ | | \/\__ | _____| /\/ | | | /___/ | | | ____________| | | | | |_/|\__________ | | ____ | ____ | |_\ \ |________\ \ ___ ___ | | \/\__| | \/\____|Q | |CLK|____/|\_______| /\/ | _____| /\/ | |___| |___| | | /___/ | | /___/ | | | ____________| | ____________| | | | | | | |_/|\__________ |_/|\__________ | | ____ | | ____ | | |_\ \ | |_\ \ | ___ | | \/\__| | \/\__|_|/Q | |________| /\/ |_________| /\/ |___| | /___/ | /___/ | ____________| | | |_/|\__________ | ____ | |_\ \ | ___ | \/\__| |D0 |_____________| /\/ |___| /___/ ---------------------------------------------------------------------------- EDGE-TRIGGERED D FLIP-FLOP _______ __| D Q |__ | | __|>CLK /Q|__ |_______| POSITIVE EDGE TRIGGER ____ _______| \ | | \/\__ | ____| /\/ | | | |___/ | | | ____________| | | | | |_/|\__________ | | ____ | ____ | |_| \ |________| \ ___ ___ | | \/\__| | \/\____|Q | |CLK|____/|\______| /\/ | ____| /\/ | |___| |___| | | |___/ | | |___/ | | | ____________| | ____________| | | | | | | |_/|\__________ |_/|\__________ | | ____ | | ____ | | |_| \ | |_| \ | ___ | | \/\__| | \/\__|_|/Q | |_______| /\/ |________| /\/ |___| | |___/ | |___/ | ____________| _ | | |_/|\__________ | ____ | |_| \ | ___ | \/\__| |D0 |____________| /\/ |___| |___/ ---------------------------------------------------------------------------- T FLIP-FLOP TOGGLE _______ __| T Q |__ T | Q(T+1) | | ___|______ __|>CLK /Q|__ 0 | Q(T) |_______| 1 | Q'(T) _____ _____ _____ _____ CLK _| |______| |______| |______| |__ ___ : : : ________ : __________ T : |__________________| : |______| : : __________________________ : ________ Q __| : : : |_____:______| : : : : : : : : : _____________________________ | ____ | |_| \ | |\ | \_ | _| \/\_| / | ____ | | | /\/ |___/ |_\ \ _______ | ___ | |/ | \___| D Q |_|__|Q | ___ | ____ __| / | | |___| |T |_|_______| \ | /___/ __|>CLK /Q|_ ___ |___| | \_| | |_______| |__|/Q | __| / | | |___| | |___/ | | ___ | | | |CLK|_____/|\_________________| | |___| | | |______________________________| ---------------------------------------------------------------------------- JK FLIP-FLOP SET/REST AND TOGGLE _______ __| J Q |__ J | K | Q(T+1) | | ___|___|______ __|>CLK | 0 | 0 | Q(T) | | 0 | 1 | 0 __| K /Q|__ 1 | 0 | 1 |_______| 1 | 1 | Q'(T) ______________________________ | ____ | |_| \ | ___ | \_ | |J |_________| / | ____ | |___| |___/ |_\ \ _______ | ___ | \___| D Q |_/|\____|Q | ___ |\ ____ ___| / | | | | |___| |K |__| \/\__| \ | /___/ __|>CLK /Q|__| | ___ |___| | /\/ | \_| | |_______| |_/|\_|/Q | |/ __| / | | |___| | |___/ | | ___ | | | |CLK|_____/|\_________________| | |___| | | |__________________________________| ---------------------------------------------------------------------------- ___ |\ |A |________| \/\__ ____ |___| | | /\/ |__| \ EXCLUSIVE OR | |/ | \__ | ____________| / | ____ | | |___/ |____\ \ ___ | | | \__|OUT| | | ____ _____| / |___| |_/|\___________| \ | /___/ | | \__| ___ | |\ __| / |B |_____|__| \/\__| |___/ |___| | /\/ |/ ADDER CIRCUITS ___ ____ |A |________________| \ |___| | | \/\_ | __| /\/ | | | |___/ | EXCLUSIVE OR | ____ | | ____ |_| \ | |__| \ ___ | \/\__| | \/\___|OUT| _| /\/ | __| /\/ |___| | |___/ | | |___/ | | ____ | | |__| \ | ___ | | \/\_| |B |_|______________| /\/ |___| |___/ INPUTS OUTPUTS Well, this looks familiar, doesn't it? The Carry output is a simple AND function, and the Sum is an Exclusive-OR. Thus, we can use two gates to add these two bits together. The resulting circuit is shown below. A B CARRY SUM 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 ___ ____ |A |__________\ \ \ ___ |___| | | | \__|SUM| __/|\___| | / |___| | | / /___/ | | | | ____ | |_____| \ ___ ___ | | \__|CAR| |B |__|_________| / |___| |___| |___/ ---------------------------------------------------------------------------- ___ ____ FULL ADDER CIRCUIT |A |_______\ \ \ ____ |___| | | | \_________\ \ \ ___ _/|\__| | / | | | \___________|SUM| | | / /___/ _/|\___| | / |___| | | | | / /___/ | | | | ____ | | | |_____| \ ____ | | | | \___\ \ ___ | | ____ |________| / | \__|CAR| | |____| \ | |___/ __| / |___| ___ | | \_/|\______________| /___/ |B |_|_______| / | |___| |___/ | | ___ | |CIN|_________________| |___| To construct a full adder circuit, we'll need three inputs and two outputs. Since we'll have both an input carry and an output carry, we'll designate them as CIN and COUT. At the same time, we'll use INPUTS OUTPUTS http://www.play-hookey.com/digital/adder.html (2 of 5)4/21/07 3:57 PM Adding Binary Numbers S to designate the final Sum output. The resulting truth table is shown to the right. Hmmm. This is looking a bit messy. It looks as if COUT may be either an AND or an OR function, depending on the value of A, and S is either an XOR or an XNOR, again depending on the value of A. Looking a little more closely, however, we can note that the S output is actually an XOR between the A input and the half-adder SUM output with B and CIN inputs. Also, the output carry will be true if any two or all three inputs are logic 1. What this suggests is also intuitively logical: we can use two halfadder circuits. The first will add A and B to produce a partial Sum, while the second will add CIN to that Sum to produce the final S output. If either half-adder produces a carry, there will be an output carry. Thus, COUT will be an OR function of the half-adder Carry outputs. The resulting full adder circuit is shown below. A B CIN COUT S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 ---------------------------------------------------------------------------- CLOCKED RS LATCH ___ ____ |S |____| \ ____ |___| | \/\____| \ ___ __| /\/ | \/\_______|Q | | |___/ __| /\/ | |___| | | |___/ | ___ | |__________/|\_ |CLK|_| | | |___| | ____________| | | | ____ | | ____ |_| \ | ___ |__| \ | \/\_____|_|/Q | ___ | \/\____| /\/ |___| |R |____| /\/ |___/ |___| |___/ The clocked RS latch circuit ---------------------------------------------------------------------------- RS LATCH ___ ____ |S |____\ \ ___ |___| | \/\______|Q | ____| /\/ | |___| | /___/ | |__________/|\_ | | ____________| | | ____ | |__\ \ | ___ ___ | \/\____|_|/Q | |R |_____| /\/ |___| |___| /___/ RS latch circuit