======================SILICON_REL================================ OP life Operational Lifetest 3 lots of 77 parts 125C at 1000 hours Or 500 hours at 150C. new product can have 1 failure with good explaination. THB Temperature Humitity Bias Test 1000 hours at 85C at 85% humitity 1 failure with a good explaination. ------------------------------------------------------------------------------------ Autoclave THB without the bias. ------------------------------------------------------------------------------------ Temperature cycle thermal expansion test, for a new package 2000 cycles at 4 weeks ,10 minutes -65C to 15C Power cycle for new package ------------------------------------------------------------------------------------ Operational Lifetest OP life For a new product you can have one failure at 125C at 1000 hours with a good explaination. Or 500 hours at 150C. This is for 3 lots of 77 parts ------------------------------------------------------------------------------------ Acccleration_Factor = EXP((E_act/K)*(1/T2-1/T1) Energy_activation = 0.9 Linear, 0.7 CMOS, 0.4 TTL K_Boltzman = 8.63E-5 to test to 1000 hours at 125 deg_C is 77000 hours at 55 degrees for E_act = .7volts which is about 10 years ------------------------------------------------------------------------------------ 3 lot 77 part 1 reject 125 1000 hours 150 at 500 ------------------------------------------------------------------------------------ Temperature Humitity Bias Test (THB) percent failure at 1000 hours at 85C at 85% humitity 1 failure with a good explaination. ------------------------------------------------------------------------------------ Autoclave is the THB without the bias. ------------------------------------------------------------------------------------ Temperature cycle .. for a new package 2000 cycles at 4 weeks thermal expansion 10 minutes -65C to 15C Power cycle .. for a new package ESD human and machine models ------------------------------------------------------------------------------------ latch up 100 mA sink/source each pin ------------------------------------------------------------------------------------ ESD human and machine models ------------------------------------------------------------------------------------ metal mitgration if exceed max current ------------------------------------------------------------------------------------ purple plaue gold metalization into aluminum at 200C brittle gold aluminum causing opens don't bond to substrate. ------------------------------------------------------------------------------------ 10 years 1000 hours at 125 deg_C for E_act = .7volts 77000 hours at 55 degrees ------------------------------------------------------------------------------------ Acccleration_Factor EXP((E_act/K)*(1/T2-1/T1) Energy_activation 0.9 Linear, 0.7 CMOS 0.4 TTL K_Boltzman 8.63E-5 ------------------------------------------------------------------------------------ humit environ silver or tin tends to form wickes across insultation 10 hr burnin 250C will get freak failures infant mortality 200c and 100 hour weed out infant mortality 1% is stiff spect 3% to 5% max HTOT 300C it take s 1000 hour for all devices to go at 250 it tkes 10,000 hours Dry ice -78C ------------------------------------------------------------------------------------ acceleration factor af = exp((1/T0 -1/Th)*Ea/kt) ea activation energry af acceleration factor oxide defects .3 -.5 silicon defects .3 -.5 corrosion .45 asssembly .5 -.7 metal migration .9 charge ijection 1.3 contaminaion 1.0 ----------------------oxide_breakedown--------------------- watch cap Breakdown see flashes as filaments as increase voltage burn out.. start at edges towards center ------------------------------------------------------------------------------------ ESD ElectroStatic Discharge ESD Latchup Latch-up is switching-on then remains on with even small voltage drops. Electromigration Moving electrons, such as found in a metal line resistance at a grain boundary will increase, and may result open contact MaX I density =5.0E+05_A/cm^2 Ipeak_max_time = 500ns Ipeak_MET1 20*A1*(MET1_Width-B1) A1= 2.03mA/um @ 7500A Iave_MET1 A1*(MET1_Width-B1) B1= 0.25 Aluminium is prone to this type failure. Vias/Contracts Max_RMS = 4.16mA @ 1um sq drawn max_I_contact 4 ma/contact max_I_via 4 ma/via Vias / plugs / contacts. Plugs are often created from different materials Copper to Aluminium, and/or a second conducting material,such as silicides, Reliability tests for this type of failure show product is initially stable at elevated temperatures, for hours or days, then resistance increases rapidly. Mechanical stress can cause cold deformation of metal lines, can create a discontinuity (an open contact) Bonding failures Kirkendal voiding. Typical of processes where a gold wire is bonded to an aluminium bond pad, after which interdifusion between the 2 metals occurs, leading to voids at the contact surface, called Kirkendal voids.used. Reliability tests for this type of failure show that the product is initially stable at elevated temperatures, for hours or days, then resistance increases rapidly, However, as contact surface becomes small, temperature causes a renewed melt-down of metals, and reduction in resistivity. The voiding process then re-occurs, cycle can continue like this almost indefinitely. AuPd (Gold Paladium) wire is far superior in preventing this failure mode. ----------------------Current_Density_BiCMOS_1u-------------------- Ipeak_MET1 < 20*A1*(MET1_Width-B1) A1= 2.03mA/um Iave_MET1 < A1*(MET1_Width-B1) B1= 0.25 Ipeak_MET2 < 20*A2*(MET2_Width-B2) A2= 2.16mA/um Iave_MET2 < A2*(MET2_Width-B2) B2= 0.32 Metal1 AlCu Ave Thickness 7500 A I_limit_Spec 5e+5 A/cm2 Min_thickness 6750 A worst_coverage 50 % FICD(+/-) 0.2 um A1 2.03 mA/um B1 0.25 Metal2 AlCu Ave Thickness 12000 A I_limit_Spec 5e+5 A/cm2 Min_thickness 10800 A worst_coverage 50 % FICD(+/-) 0.25 um A2 2.16 mA/um B2 0.32 max_I_contact 4 ma/contact max_I_via 4 ma/via BiCMOS_1u Metal uses Al/Cur btween Ti/TiN pulg liner and TiN arc MaX I density 5.0E+05_A/cm^2 Ipeak_max_time 500ns Metal 1 7500_Ang AlCu Ipeak1 max 20*A1*(W-B1) A1= 2.03mA/um Iave1 max A1*(W-B1) B= .25 Max_I_Min_MET1 2.13mA @ 1.3um_drawn Metal 2 12000_Ang AlCu Ipeak2 max 20*A2*(W-B2) A2= 2.16mA/um Iave2 max A2*(W-B2) B2= .32 Max_I_Min_MET2 2.98mA @ 1.7um_drawn Vias/Contracts Max_RMS = 4.16mA @ 1umsq drawn Idsat 0.41mA/um Nch 20uM*.41 8mA needs 2.03*(5-.25) BiCMOS_1u uses aluminum/copper btween Ti/TiN pulg liner and TiN arc MaX I density =5.0E+05_A/cm^2 Ipeak_max_time = 500ns Metal 1 7500_Ang AlCu Ipeak < 20*A1*(W-B1) A1= 2.03mA/um Iave < A1*(W-B1) B= .25 Max_I =2.13mA @ 1.3um_drawn Metal 2 12000_Ang AlCu Ipeak < 20*A1*(W-B1) A1= 2.16mA/um Iave < A1*(W-B1) B= .32 Max_I =2.98mA @ 1.7um_drawn Vias & Contracts Max_RMS = 4.16mA @ 1umsq drawn highest current density is going to occur at the output stage metal. This involves the VCC, Output, and GND metal paths. The BiCMOS_1ucbi spec lists the following equations to determin maximum metal current. ^ Vcc =5V /_\ | R |__/\ ___ \/ | |___|\ RL = 600ohms __/\ ___| |+\ _|_ \/ R | \___________/\ ____ \ / | / | \/ | V gnd __|-/ | 8.33mA ->_|_ | |/ R | \ / gnd |____/\ ___| V \/ Ipeak_MET1 < 20*A1*(MET1_Width-B1) A1= 2.03mA/um Iave_MET1 < A1*(MET1_Width-B1) B1= 0.25 Ipeak_MET2 < 20*A2*(MET2_Width-B2) A2= 2.16mA/um Iave_MET2 < A2*(MET2_Width-B2) B2= 0.32 Since Metal2 can handle more current than metal1, if the minimum width is in metal1, this will therefore have the worst case current density requirements. Where Metal1 connects to pads ____ Wostcase Current density | MET1 14um @ 10Vias V __| | ______ | `--' ___ | |ESD_CELL |PAD| | <= VCC_pad,OUTPUT_pad,GND_pad | |___| | |_______,--.______| The worst case current densities therefore happen where metal1 connects to all the pads. This metal is 14um wide. From the equations above, this metal should be able to handle.. Ipeak_MET1 < 20*2.03*(14-.25) = 558.25 mA Iave_MET1 < 2.03*(14-.25) = 27.91 mA This maximum current rating corresponds to a current density of 5E+5 A/cm2 under the conditions listed at the end of this email. ^ Vcc =5V /_\ | R |__/\ ___ \/ | |___|\ RL = 600ohms __/\ ___| |+\ _|_ \/ R | \___________/\ ____ \ / | / | \/ | V gnd __|-/ | 8.33mA ->_|_ | |/ R | \ / gnd |____/\ ___| V \/ So for the above application, the current density is about 1/3 of the limit or in other words about .. Current Density = 1.5E5 A/cm2 ------------------------------------------------------------------------------------ Corrosion Corrosion problem areas in fab are numerous, Examples are Metal lines corrosion, often caused by water vapour contamination of Chlorine metal etch systems, or NH4OH corrosion of Tungsten layers during cleaning. EEPROM determining the long-term data retention of memory cell, tested at high temps and extrapolated to user conditions. and erase cycles, with a goal of keeping tunnel oxide leak and breakdown free. Passivation pinhole test Small holes in the final passivation layer can cause reliability problems, tests are designed to show that #holes /cm^2 does not exceed a pre-determined level. ======================SILICON_ABUSE_TESTS====================== 1: Take the output to voltages that are outside of the supplys, such as might happen when driving an inductive load. Does it get in trouble? 2: Pulse the power supply on and see how long it takes to become operative. Change the input and output voltages BEFORE applying the power supply. Does this cause problems? 3: Overdrive the amplifier and see what it does at both the input and output. 4: Measure settling time to 0.1% and 0.01%? Do this at different loads. Does ithave long thermal tails? 5: Look at distortion vs Vo, frequency, load and Vs. 6: Check the short circuit protection. plug in hot socket plug in backwards square wave to observer ringing ------------------------------------------------------------------------------------ abuse tests output exceed rails L load by 100ma current input exceeds rails phase reversal by 1v voltage input exceeds rails latchup/funnies by 100ma current plug in backwards smoke test 3Amp supply what ever kills parts smoke test 3Amp supply output clipping how recover overdrive/freq Zout stablity any load anything funny scope waves cap loads oscillation current limit waveforms kill a part , -6volt at neg intput freeze spray open lid latch up = warm, does not kill part phase reversal exceed rails good to .7 volt clipping rail funnies slight vissible hang on 10KHx pulse power supply see when operational as shutdown PHASE_REVERSAL forward biasing ESD structures as unity follower ___ | |___|\ |___| |+\ ___ | \_______| | Unity gain Buffer | / | |___| application __|-/ | | |/ | |___________| ^ /|\ Actual Ouput when ESD diode turns on | __.....__ ...............................Vcc | __/ \ _ | _/ \_ _ _|/ _ _ _ _ _ _ _ _ _ \_ _ _ _ _ _ _ _ _ _ _ _ \ | \_ .... _/ / | \__ : : __/ | \_: :___/.........Vee | Would like output to clamp at rails when input exceeds rails. Normaly true as long as ESD diodes to substract not tudrned on. ------------------------------------------------------------------------------------ Maintenance Performance indicators MTBF: Mean Time Between Failures, in hours MTTR: Mean Time To Repair, in hours MTBC: Mean Time Between Cleans, in wafer processing time MTTC: Mean Time To Clean, in hours TTPM: Time To Preventive Maintain, as a % of total time MTBA: Mean Time Between Assists, or stoppages,in hours MTTA: Mean Time To Assist, in minutes MTTQ:Mean Time To Qualify,for release to production,hours NPT: Non Productive Time, as a % of total time. Utilization: Percent of the available time which is used for processing wafers Maintenance planning The concepts of Weekly, Monthly, Quarterly, and Yearly maintenance, are usually not well suited to semiconductor equipment, often results in unnecessary activi ties, and can contribute to reduced productivity. It is often better to define: CM: Cleaning Maintenance, and PM: Preventive Maintenance The basis for all planning of maintenance activities should be the time unit of the most frequent maintenance activity. This is usually the CM, Cleaning Maintenance, or the basic PM. It is common for this time unit to be based on # wafers processed, or the total wafer processing time, or days / weeks. The following illustrates a simple, yet effective, maintenance planning scheme. More complicated schemes are of course possible. CM1: Partial CM, the most frequent maintenance activity, a simplified clean. CM2: Complete CM, a procedure for a complete system clean. PM1: Simple PM, a procedure for check and tune / adjust, simple equipment tuning, whose frequency is a multiple of CM1 (from 1 and greater) PM2: More thorough PM, consumables replacement, not normally replaced during CM activities. PM3: Complete PM, including replacement of parts with a finite life expectancy Below is the maintenance plan, showing these concepts. (Y is Yes). Every 2 periods, CM1 is done. CM2 and PM1 are done together, every 4 periods. PM2 is done every 8 periods, and PM3 every 16 periods. Period CM1 CM2 PM1 PM2 PM3 1 Y Y Y 2 3 Y 4 5 Y Y Y Y 6 7 Y 8 9 Y Y Y 1 0 11 Y 12 13 Y Y Y Y Y 14 15 Y 16 17 Y Y Y Predictive maintenance Promote economical PM through engineering analysis Develop methods to predict failures Analyse feedback from all PM activities, to determine if there are additional areas requiring maintenance, or to determine unnecessary maintenance or exchanged parts. Techniques CCA: Critical Components Analysis Identify and take action on parts which have a high risk of failure, and would impact productivity Many such parts exist, but this analysis should focus on the parts with the highest risk, measured as hours downtime /year, and/or cost /year. AssemblyPartFailure mode ExpectedLifetimeParts Delivery TTR Risk (hr/y) Cost Risk ($/y) PM plan PM time PM hr/y PM $/y Pump Rotor Corrosion 6 months 4 hrs 4hrs 16 hrs $2000 $4000 ? ? ? ? Chamber Electrode Erosion 25k min 0.5 hrs 16hrs 66 hrs $2000 $8000 PM2 20k min 10hrs 10000 Transfer Belt Wear / tear 100k wafers 0.5 hrs 4hrs 5 hrs $100 $200 PM3 60k min 2hrs 200 Pareto analysis Pareto charts show frequency of individual contributors to an indicator or performance. Numerous charts are possible. Pareto of Utilization, showing the contributions of Preventive and breakdown maintenance, brief stoppages, and non-productive time, sub-divided into individual causes when known. Pareto of defectivity, showing causes of incidents Pareto of equipment problems, which can usually be partially generated automatically, such as equipment warnings and alarms. Contract services The complexity of the equipment often requires that the equipment supplier, or a third party, be contracted to ensure that all failures can be quickly diagnosed and repaired, and to help with highly technical issues regarding the equipment. The best method to deal with this is through a Service Level Agreement (SLA), where service to be provided is clearly identified. The objectives of the support required, usually called Key Performance Indicators (KPI) day-to-day requirements for CM and PM support Breakdown, and on-site / on-call support for unexpected failures An escalation plan for communicating at management level of inappropriate support for the current situation Details of additional support required:training, upgrades, equipment and process engineering, software, etc. Parts management responsibilities. Billing and Accounting information Chart techniques Uptime and equipment Utilization In the graph below are shown the equipment process time (green bars), the equipment idle time (clear bars), and equipment utilization (blue line).MTBF,MTTR In graph below are shown equipment MTBF(red line), MTTR (green line), both measured in hours (left axis)Also shown are # of system down events, either scheduled downs(green bars) or unscheduled down (red bars), on the right axis. The MTBF and MTTR data are calculated according to SEMI spec,requiring 13 weeks of data.data collection began in first week of 1998, and correct data becomes availweek 13.Analysis of trends above equipment example shows that uptime of system been increased to above 90%, by reducing number of unscheduled down events(unpredicted machine faults), by introducing regular preventive maintenance(scheduled down events).Utilization of the equipment is trending lower, because high uptime allows better distribution of work load on system. Sample Productivity Value (PV) calculation Download sample file PV file, TPM_PV.xls (21kb, excel_95 or higher) Productivity Value of Poly Etcher: PV= Q x U x E / C = 2.22 x 0.66 x 0.81 / 12.12 PV = 0.0972 Thus the equipment and engineering groups now have baseline performance value of 0.0972 for Poly Etcher, use same calculations to evaluate all engineering efforts. calculation requires priorities of fab and/or department responsible, be determined, so that appropriate weighting to PV factors are used. Once determined, possible to compare systems using same priorities, thus concentrate efforts further. calculation is easy, and should not take more than a few minutes for each equipment or equipment family. ------------------------------------------------------------------------------------ Reliability of ICs Reliability = probability working over time period. Accelerated reliability testing Reliability is often measured in # failures within hundreds or thousands of hours. , accelerated tests are extrapolated for normal operating conditions. A sample accelerated reliability program: DHTL/SHTL:Dynamic/Static HighTempLife.150C 168/1000hr DLTL:Dynamic LowTempLife. -40C. Spec test for failure , esp. hot carrier degradation. HAST:HighlyAcceleratedSteam Test 132C, humidity = 85% TMCL: TeMperature Cycle Test. -65C to 150C PPOT: Pressure Pot Test. 120C, Relative humidity = 100% THS: Temperature Humidity Bias Stress. 80C humidity = 85% Normal distribution: Classic with a median and a standard deviation. Lognormal distributi Similar to the normal distribution, with a logarithmic time base Weibull distributio Capable of modelling a large variety of distributions with 2 variables, F=1-exp(-(a*t)^b), which becomes ln(-ln(1-F))=b*ln(a)+b*ln(t), which is a straight line on a log(time) x axis. bathtub curve expectation of failure rates follows a familiar , where the failure rates initially decrease from high levels, stabilise for a long period at low levels, and finally increase as the ICs wears out. Reliability+Yield very high levels (<10 failures per million,1k hours ) general major cause of failures are particles. accurate model Reliability R=1-(Y/M)^a M is maximum expected yield for process and can also allow for clustering of defects. typically above 90% a is the main parameter used to fit the model to experimental or actual data. a = Dr / Dy , Dr product reliability defect density of yielding die Dy is die yield defect density. Reliability can be improved by improving the Yield, ======================CMOS_LATCHUP============================================== ^ /_\ Vcc | _/\ /\_______________ |_______/\ /\____ | \/ | | | \/ | | Gate | _|_ | Gate | | _|_ | \\\ | _|_ | _|_ _|_ |___| _|_ _|_ |___| _|_ _|_ _|___|__|___|_|___|_|___|___|___|_|___|_|___|_|___|___ | P+| | N+ |<--| N+ | | | P+ |++>| P+| | N+ | | \___/ \____/ \___/ | \___/ \___/ \___/ | 700mV | Vcc-700mV | electrons \ holes NWELL / SUBSTRATE \_______________________/ In a CMOS circuit, it is common to have a Pchannel source connected to Vcc while a Nchannel source is connected to ground. An example of this would be an invertor. The Pchannel device would sit in a Nwell bulk that is also biased up to Vcc. Likewise, the Nchannel sits in ground biased substrate. If the resistance to the biasing of the both the Nwell and substate are no lower, there exists an opportunity for a latch up to occur. ^ /_\ +5V _____|__________ | | -> | PNP`|______/\ /\_| _'| | \/ | |________ | | |_________ | | _| __/\ /\_|__|' NPN | \/ |`-> |________________| | _|_ \\\ The circuit above shows the "classical" SCR schematic. When on, the loop gain is the product of the two betas. Emitter base resistors are commonly added to define the conditions under which the SCR is On or off. ^ /_\ Vcc | _/\ /\_______________ |_______/\ /\____ | \/ | | | \/ | | Gate | _|_ | Gate | | _|_ | \\\ | _|_ | _|_ _|_ |___| _|_ _|_ |___| _|_ _|_ _|___|__|___|_|___|_|___|___|___|_|___|_|___|_|___|___ | P+| | N+ | | N+ | | | P+ | | P+| | N+ | | \___/ \____/ \___/->|<+\___/ \___/ \___/ | 700mV \ `-->|<++' / Vcc-700mV | electrons`--->\<+++' holes NWELL / SUBSTRATE \________________________/ Latch up is usually tested by forward biasing an ESD diode with 100mA. The latch up requires that both a P+ and N+ junction needs to be forward biased. The P+ junction will eject holes into substate. The N+ junction ejects electrons into the Nwell. When the IR drop due to the ejection rates reachs a diode voltage, the SCR will latch up. It is standard linear practice to provide as many substate and Vcc tub connections as possible. This practice should discourage latchup. ====================MATH==================================== For those who like pictures... |-----99.9937%----| | |----99.73%---| | | | |--95.5%--| | | | | | |-68%-| | | | | | | V V | | | | | | xXXXx | | | | | V XXXXXXX V | | | V XXXXXXXXX V | V XXXXXXXXXXX V __..xXXXXXXXXXXXXXx..__ | | | | | | | | | 4 3 2 1 0 1 2 3 4 1 sd =1mv yield for single is 68% yield for dual is 68% of 68% ....47% If all limits set for +/- 3 sd. Total yield = (.9973)^(number of tests) Total yield = (.9973)^(50 tests) = 87% If all limits set for +/- 4 sd. Total yield = (.999937)^(50 tests) = 96.8% |<----------15.8%----> V |<--------2.2750%--> xXXXx | |<------0.1350%--> XXXXXXX V | |<---0.0032%---> XXXXXXXXX V | XXXXXXXXXXX V __..xXXXXXXXXXXXXXx..__ | | | | | | | | | 4 3 2 1 0 1 2 3 4 ------------------------------------------------------------------------------------ TVS Silicon transient voltage suppressors are clamping devices limit voltage spikes by low impedance avalanche breakdown used to protect sensitive components from lightning,inductive load electrostatic discharge. leakage current (ID), and capacitance should be "invisible" VWM reverse standoff voltage approximates operating voltage is normally 10% below breakdown voltage. Most specified with a 10/1000us surge waveform (10us rise to peak and 1ms decay to one-half peak), TVS families normally specified in kilowatts of peak pulse power (PPP) ranging from 15kW down to 300W. Most TVSs are rated for 10/1000us non-repetitive pulses short pulse widths,sustain higher pk pulse currents (IPP) For longer pulses, TVS will withstand lower IPP values. TSPDs Thyristor surge protective devices are avalanche triggered used to protect from induced lightning. TSPDs protect by switching to a low on-state voltage (VT) of a few volts, thus providing a "crowbar" effect with high current capability (up to 200A). available bidirectional or unidirectional V(BR) TSPD breakdown voltage 20% to 30% greater than the maximum repetitive off-state voltage (VDRM). VDRM is the normal operating voltage level. Transition to on-state voltage (protective mode) is initiated at device s maximum breakover voltage (V(BO)) Once in on-state conduction, must drop below minimum holding current (IH) to restore to nonconduction after the transient has subsided. Minimum holding current from 50mA to 250mA @ 25oC and decrease by 60% at 100oC, advantage of TSPD is low on-state voltage after triggering provides much higher surge current capability ..40 most ICss susceptible to ESD levels less 2k V Your fingertip can t feel 3,000 V, but your computer can, so you can cause damage without knowing it. TPM Total Productive Maintenance: developed by Japanese companies, and the Institute of Productive Maintenance Technology was founded by Yoshikazu Takahashi. TPM goal to focus on increasing productivity. motto: Engineered For Productivity (EFP), not Engineered To Perfection (ETP) Move from a reactionary to pro-active work style PV: Productivity Value of equipment, PV= Q x U x E C Q: Quality of Process U: Utilization of Equipment E: Equipment Environment C: Cost of Operation and Ownership (usually known as COO) Q Quality of Process Capability ability of the equipment to perform process required. Range is 0-1. Stability SPC of the process, Cp and Cpk Yield Impact Level of Defect Density from baseline equipment ROQF: Rate Of Quality Failures, per 1000 wafers Rework rate, per 1000 wafers Scrap rate, per 10000 wafers U Utilisation of Equipment Throughput Measured in wafers / hr, Availability Measured as a %, time available Preventive Maintenance Breakdown maintenance Brief stoppages ======================SILICON_DEFECTS===================== Various crystal defects in a simple cubic lattice a) interstitial impurity ion | | | | | | | -0--0--0--0--0--0--0- | | | |A | | | -0--0--0--0--0--0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | edge dislocation | | | | | | | -0--0--0-0-0--0--0- | | \ / | | -0--0--0--0--0--0--0- | | | | | | -0--0--0--0--0--0--0- | | | | | | self-interstitial | | | | | | -0--0--0--0--0--0--0 | | | |0 | | -0--0--0--0--0--0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | coherent precipitate of substitutional atoms | | | | | | | -0--0--A--A--A--0--0- | | | | | | | -0--0--A--A--A--0--0 | | | | | | | -0--0--0--0--0--0--0- | | | | | | | small dislocation loop formed by agglomeration of self-interstitials | | | | | | | -0--0--0-0-0--0--0- | | \ A / | | -0--0--0--0--0--0--0- | | | | | | -0--0--0--0--0--0--0- | | | | | | substitutional atom widening the lattice | | | | | | | -0--0--0--0--0--0--0- | | | | | | | -0--0---0-A-0---0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | vacancy | | | | | | | -0--0--0--0--0--0--0- | | | | | | -0--0--0 0--0--0- | | | | | | -0--0--0--0--0--0--0- | | | | | | | small dislocation loop formed by agglomeration of vacancies | | | | | | | -0--0--0-0-0--0--0- | | \ / | | -0--0--0--0--0--0--0- | | | | | | -0--0--0--0--0--0--0- | | / \ | | -0--0--0-0-0--0--0- | | | | | | | substitutional impurity atom compressing the latticelO | | | | | | -0--0--0--0--0--0--0- | | | | | | | -0--0-0---A---0-0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | Point defects 0 0 0 0 0| 0 0 0 0 0 0 0 | 0 0 0 0 0| 0 0 0 0 0 0 _ 0 0 0 _/ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Schottky defect ___ 0 0 0 0 0 0 0 0 0 0/ 0 0 0 0 0 0 0 0 0 0 0 |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 interstitial arriving from surface 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --- > 0 0 0 0 / 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c) Frenkel defect. Intrinsic point defects important in kinetics of diffusion. diffusion of many impurities depends on the vacancy concentration. low packing-density of the diamond lattice (34% versus 74% for a fee lattice) implies large spaces between atoms (interstices) which atoms of same size can be placed without shifting of neighboring atoms structural condition of the silicon lattice favors incorporation of interstitials, why Si lattice fewer vacancies than metal lattices self-interstitial | | | | | | -0--0--0--0--0--0--0 | | | |0 | | -0--0--0--0--0--0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | extrinsic point defects, involving foreign atoms. non-Si atoms occupy lattice sites, defects referred to as substitutional impurities. bonafide point defects, atoms are larger or smaller crystalline regularity perturbed. substitutional atom widening the lattice | | | | | | | -0--0--0--0--0--0--0- | | | | | | | -0--0---0-A-0---0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | Impurity also occupy non-lattice sites, called interstitial impurities. | | | | | | -0--0--0--0--0--0--0 | | | |A | | -0--0--0--0--0--0--0- | | | | | | | -0--0--0--0--0--0--0- | | | | | | | To be electrically active, atoms usually must be located on lattice sites. inherent solubility of impurity in silicon crystal. is a maximum specific concentration depends on the element and temperature solubility most impurities increases up to a temperature, then decreases as approaches its melting point. known as retrograde solubility. dislocations form by growth and multiplication of dislocation loops in the bulk, or from dislocations generated at the surface in response to stresses created in crystal. edge dislocation | | | | | | | -0--0--0-0-0--0--0- | | \ / | | -0--0--0--0--0--0--0- | | | | | | -0--0--0--0--0--0--0- | | | | | | Stresses can arise i a) diff expansion due to temp variations in crystals''; b) intro substitutional impurities cause stresses between doped and undoped crystal regions called misfit dislocations.); c) compressive stresses from volume mismatches arise during some precipitation events d) coefficient of thermal expansion stresses caused by layers present on surface of crystal7 involves growth of thermal oxide and suppression of oxidation on other by nitride layers. Dislocation causing stresses result primarily from tensile stress silicon nitride, and volume expansion of oxide formed in walls.) stresses arise in a variety of ways seed crystals undergo high thermal stress when immersed into Si melt during single crystal ingot exterior of seed crystal is brought to melt temperature, interior much cooler. Stresses resulting from expansion at surface and interior of seed crystal induce dislocations lead to plastic deformation of crystal. (Plastic deformation is permanent deformation of material that remains after stress released. Elaitic deformation, lost upon release of stress. Plastic deformation occurs when elastic limit [or yield strength] is exceeded.) Dislocations in wafers induced by thermal stress during furnace operationss. Upon removing wafers from furnace, edges of wafers cool faster wafers are held vertically and spaced closely in wafer boats. edges radiate heat to cooler surroundings stress S from uneven cooling S = cr ff T cr= coeff thermal expansion silicon 4e6 cm /cm'K, ff= Youngs modulus ( 1.5 x 1012 dyn lcm2, T = temperature difference between edge and center (temperature gradients in cooling wafers can reach >150'C). If stress exceeds yield strength dislocations will form. stress from 150'C gradient 0.9 x 10' dyn lcm2, larger than yield strength (0.45e9 dyn /cm2 850'C, thus introduce dislocations. yield strength of CL Si wafers is impacted by the presence of impurities, as oxygen. Dislocations can climb and glide. Climb occurs when point defects are absorbed by the dislocation line. Thus, if a self-interstitial is captured, an edge dislocation moves as shown in Fig. 5a, while the absorption of vacancy causes line to climb in opposite direction. Dislocation loops also change size by climb-type events (absorption of point defects). Movement of the dislocation in the surface defined by its line and | _____| |/ | | | | | | | | | | | | . ._/ |. _- | - Typical characteristics of single-emitter test transistor (emitter area 3 x 8 m) with emitter collector short showing up in ICEO IVCE (---) ICE /VCB ( ). and IEB IVEB (...) are "hard"57 _________ p / ___/____ _________ n | / p \/_____ ___/____ _________ n | \/___ n \/_____ p ___/____ b) Schematic of enhanced emitter diffusion model explain collector-emitter pipe formation CRYSTAL DEFECTS ON DEVICE PROPERTIES T influenced by crystalline defects include: a) leakage currents in p-n junctions; b) collector-emitter leakage currents in bipolar c) minority carrier lifetimes; d) gate-oxide quality; e) threshold voltage uniformity in MOS devices; f) resistance to warpage wafers during thermal process Leakage Currents precipitates and dislocations increase pn junction leakage. transition metal precipitates in pn junction produces leakage due to mid-gap energy levels at low voltages, and a "soft" leakage component at higher voltages Dislocations and thereby extrinsic stacking faults that cross pn junctions, The formation of generation-recombination (g-r) centers defect sites junctions, and the decoration of dislocations Collector-to-emitter leakages have been correlated with dislocations from emitter to collector. If dislocation decorated with metallic impurities, permit significant current between collector and emitter dislocation role in enhancing diffusion along dislocation during emitter formation can lead to emitter-collector pipes, precipitates contributes to locally retarded dffjsion of dopant atoms in shallow double-diffused structures. dopant appears not to diffuse as rapidly in region of precipitate, forming a localized spike pointing upward toward the wafer surface2 precipitate apparently dissolves during first diffusion. second diffusion is thus effected by precipitate, locally narrow separation of emitter and collector at spike causes excessively large reverse currents. not expected to occur in ion-implanted devices. Minority Carrier Lifetimes mean time spent before they recombine Gate Oxide Defects in silicon subscrate MOS devices: 1) oxide leakage current; 2) oxide breakdown voltage. both correspond to stackig faults at silicon substrate generated by metallic contamination during oxidation. correlate with high defect density on wafer surface. ------------------------------------------------------- tau_p 1/(sigma_p*v_th*N_t) lifetime in low level injection N_t concention of centers of recombination v_th sqrt(3*k*T/m) = ~ 1e-7cm/sec thermal velocity sigma_p capture cross section n N_c*exp( (E_c - E_f)vt) p N_v*exp( (E_f - E_v)vt) Fermi Dirac 1/(1+exp( (E - E_v)vt) ) Fermi Dirac distribution n_i^2 N_c*N_v*exp ( -E_g/vt) intrinsic carriers Phi_Fn vt*ln(N_D/n_i) Phi_Fp vt*ln(N_A/n_i) Phi_T Phi_Fp + | Phi_Fn | built in pn junction V q*C_B*W^2/(2*K_s*e_0) W sqrt( 2*K_s*e_o*Phi_T/(q*N_A) ) depletion width I_R I_gen + I_sh + I_surface reverse leakage I_gen q*n_i*W*Area/tau_g generation leakage funct_of 1/tau_g funct_of Num_traps I_gen(V) I_gen_0*sqrt(V) from W I_gen(T) I_gen_0*exp(-E_g/(2*K*T)) from ni I_sh (q*n_i^2*Area/N_D)*sqrt( D_n/tau_r) shockley component funct_of sqrt(Num_traps) "diffusion current" I_sh(T) I_sh_0( -E_g/( K*T)) n_i ni_i_0*exp(-E_g/(2*K*T)) T_c when I_gen(T) = I_sh(T) at or below room D_n v_t/mu_n 34cm2 diffusion coefficent v_t K*T/q thermal voltage mu_n 1300cm^2/V-s @ room mobility D_p v_t/mu_p 13cm2 diffusion coefficent mu_p 500cm^2/V-s @ room mobility L_p sqrt(D_p*tau ) diffusion length tau 34u -> 2000u lifetime I_surface 4e9/cm2-V about surface state leakage n n n n n n ____________ Ec ............ Ef N type _____________Ev p n n ____________ Ec ............ Ef P type _____________Ev p p p p p p Ef Fermi Potent where prob of electron is 50% f(E) 1/(1+exp( (E-EF)/KT )) Tau TF = Wb^2/(2*Diff_b) vt KT/q Thermal energy KT/q Diffion/mobitity ======================SILICON_BREAKDOWN=========================== watch cap Breakdown see flashes as filaments as increase voltage burn out.. start at edges towards center %_of_Isat At given voltage given percent Isat forms holes/electrons I_leakage Isat + Isat*P% + Isat*P%^2+.. Isat/(1-P%) P% (V/Vbeakdown)^3 I_leakage Isat/(1- ( (V/Vbeakdown)^3 ) ) Pbeta% (Beta+1)*P% if beta get into the picture Vcbo Vcbo/((1+Beta)^sqrt(1/3)) Breakdown BVbco_V 95*(rho_epi_ohm_cm)^(.722) BVceo_V BVbco_V/( (Beta_max+1)^(.25) ) BVbco_TLV 36*(w_um)^(.861) BVbco_thickLimited_V ======================SILICON_ESD_INFO=============================== Human Body Model HBM ___ Rs => 1.5K |Vs |__/\ ____ ___/\ ____ |___| \/ \ \/ | Auto = 4K to 20K | _|_ 2000V _|_ |DUT| ___ 100pF |___| 2KV = perception pain | | ___ | | |GND|____________|___________| tau = 150ns |___| I = 2A @ VS=2K 2A | 10ns 15% ringing | ~~-_ | / -_ | / -_ |/____________ time constant 150ns Number devices Min 3 each stress test each pin zap each to VCC shorted to GND Class 1 0 to 1999V Class 2 2000V to 3999V Class 3 4000V or above Machine Model MM Like handler Japanenes model 750nH + 25ohms ___ Rs => _ _ _ |Vs |__/\ ____ ___/ \/ \/ \__/\ _ |___| \/ \ () () \/ | | _|_ 200V _|_ |DUT| ___ 200pF |___| | | ___ | | |GND|____________|___________________| tau = 50ns |___| I = 1.7A @ VS=200V | 30ns | : 1.7A | _--_ : | / \: __ |/______|____/_ \__/ time constant 50ns Charge Device Model CDM ___ Rs => 1ohms |Vs |__/\ __ __/\ _ |___| \/ | ___ / \/ | Charge each pin |_|DUT|__| | then short to ground 1500V |___| | ___ 200pF | Like factories | | ___ | | |GND|____________|_______________| |___| I = 7->20A @ VS=1500V | | 1.7A | _--_ 7 -> 20A <1ns | / \ |/______|____ time constant 400ps ESD HBM TESTER ___/\ __ | \/ | |__||_____| DUT 23nH| ||0.8pF| 6.3nH ___ _ _ _ | _ _ _ | _ _ _ ___ | |__/ \/ \/ \|/ \/ \/ \|/ \/ \/ \_______________| | |___| | () () () () () () | | _|_ |___| _|_ 2.2nH _|_ | 1.5K ___ ___9.3pF ___ |_/\ ___| 0.7pF | 6.3nH | \/ _|_ 100pF ___ | _ _ _ _ _ _ _ _ _ | 2.5pF ___ ___ | |_|/ \/ \/ \_/ \/ \/ \_/ \/ \/ \|___________|__| | |___| () () | () () | () () |___| | 6.3nH | 0.8pF| 6.3nH tester gnd _|_ |___||____| /// | || | |_/\ ____| ESD HBM TESTER simulator \/ ----------------------Common_failures-------------------- High_field Oxide rupture most common small crater formed under gate material can happen at sharp corners Localize_heat filamentation most common silicon melts, Si resist down 1/30, thermal runaway refered to as second breakdown In bipolar BE most common increase in reserve leakage current of pn junction worst case junction shorted. Junction spiking the same except melting includes aluminum which lowers melting point to 577C as oppose to 1415C for silicon. high_current_density Thin film fusing common oxide charging least common.. because oxide damage happens too Contamination Bakeable leakage at input Hot electrons Bakeable leakage at output rho 85 mohms/sq thick 0.5u metal melts 653 J/gm at 653 C metal melted 1048 J/gm at 660 C metal vaporize 3172 J/gm at 2476 C width J/gm 10u 10,000 15u 2,177 20u 672 High_field ^ /|\ I | physical change in | oxide microstructure c | / u | |_______________ Rupture point r | Dead | r | | e | | Non destructive n | | Conduction t |______________|______________\ Capacitor Voltage / Most common is rupture of oxide which has a IV curve as is shown above. ______________ ___ _|_ | | | High field /// | |___| Oxide rupture most common ________| | Source| Gate | Drain | small crater .1u under gate __|__ __|___ __|__ ______|_ _|__|_____v|__|_ _|______ | N+ | | N+ | OXIDE DAMAGE \________/ \________/ 1nA -> 10uA Substrate possible to see this damage. damage is also sensitive to the oxide thickness and the amount of time voltage is applied. Oxide Breakdown versus time and thickness 1sec ................................... | . . . | 55A . 100A . 200A . | . . . | . . . | . . . 1msec |......55A........100A........200A... | . . . | . . . | 55A. 100A . 200A . | . . . | . . . 1usec |..........55A........100A......200A.. | . . . | .55A 100A . | . 55A . 100A 200A | . . . | . . . |____________________________________ 0V 10V 20V 30V Breakdown voltage Even before breakdown, the oxide can be modified as is shwon below/ Oxide Degraded 30V .................................... | . BD BD . | . BD TS . | BD TS. . | Break BD TS . . | Down BD . TS . . 20V |.......BD......TS................... | BD . TS . . | BD .TS 10mV Threshold shift. | BD TS . . | BD TS. . . | BD TS . 100nsec Pulse . 10V |...BD.TS............................ | . . . | . . . | . . . | . . . | . . . |____________________________________ 0A 100A 200A 300A Thickness high_current_density ^ /|\ I | | c | Oxide charge injected into oxide u | physical change in oxide microstructure r | r | / e | / Strong Avalanche n | _ t |_______-____________\ Avalanche Voltage / When electrons have lot energy, hot electrons enough energy to penetrate the oxide barrier. ______________ ___ Hi I +d chargeinjection _|_ | | | local heat/oxide rupture /// | |___| ________| | can see small notches Source| Gate | Drain | at drain/gate from hot __|__ __|___ __|__ spots caused byelectron ______|_ _|__|______|__|_ _|__trapped in gate | N+ | `-_ N+ | \________/ \________/ 5u drain spacing to contacts help 1nA -> 10uA Substrate JUNCTION EDGE DAMAGE Having electrons inside the oxide can create localize heat or oxide rupture. Localize_heat ^ /|\ I | | Damage by local heating c | / u | |____ Second Breakdown r | Dead / r | / e | / n | _ t |-______________________\ Foward Diode Voltage / Once silicon melts, all bets are off.resistance drops by a factor of 30 and a small area goes into thermal runaway. ______________ ___ _|_ | | | Localize heat /// | |___| silicon melts ________|___ | Si resist 1/30 Emitter| Base | Collector | thermal runaway __|__ __|__ __|__ _________|_ _|___ __|_ _|_______|_ _|_____ | | | N+ | | | N+ | | | | \________ / Base | \________ / | | \ \| / | | \______________________/ | | _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ | |/ \| \_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ / FILAMENTATION For Bipolar transistors, runnawayoften called second break down. destruction involve a filament in the emitter base junction because where the TC effects are most unstable. ^ /|\ I | | Damage by local heating c | / u | |_______________ Second Breakdown r | Dead | r | / e | / n | _ Breakdown t |_____________-_______________\ Reverse Diode Voltage / ______________ ___ _|_ | | | Localize heat /// | |___| si melts->thermal runaway ________| | al lowers melting to 577C Source| Gate | Drain | __|__ __|___ __|__ JUNCTION SPIKING ______|_ _|__|______|__|_ _|______ | N+| | N+| / | \________/ \___|/___/ / > 50uA Substrate ______________ ___ _|_ | | | Localize heat /// | |___| ________| | Source| Gate | Drain | Can see metal filament hole __|__ __|___ __|__ when etch away metal ______|_ _|__|______|__|_ _|______ | \`------------' / | \ N+ `-------------' N+ | METAL FILAMENTATION \_______/ \________/ 1uA -> 100uA Substrate For MOS devices, if the aluminum melts, the melting point gets much lower and a metal filament can grow and be seen. often time the extra steps taken in processing to reduce hot electrons can also further degrade ESD preformance Silicides reduces contact resistance But lower thresshold preformance because more current flows in a smaller silicide area since the ressistance of silicide to silicon is high. (Drop by 50%) LDD reduces Hot electron degradation LDD also may reduce the area which power is dissipated. Snap_Back_Protection It is the lateral NPN that clamps the ESD voltage. When currents get high enough, enough holes get generated in the substrate to over come the resistance to ground and the NPN goes into the Vceo mode. _____________ ___ _|_ | | | /// | |___| ________| | Source| Gate | Drain | Holes into Base from CB __|__ __|___ __|__ leakage ___|_ _|__|______|__|_ _|_Base/Bulk voltage rises | N+ |---> | N+ |Electrons emit fromemitter \________/--> <++\_______/ Thresshold voltage lowered Substrate ___ | | |___| |_____________ __| | || _| ||___________ _|' NPN __|| | |`-> | ||-> _/\ _| | | | | \/ | |_____|__|___________| _|_ /// One key detail is where the snap back voltage happens. Hopefully maximum oxide voltage is not exceeded before this point is reach. ^ /|\ I | | c | / u | |_______________ Second Breakdown r | Dead | r | / e | SnapBack/ SnapBack n | Voltage|______Thresshold t |_____________________/_______\ Snap Back Breakdown Voltage / The present ESD structure is shown below. PMOS device being used as a capacitor and the gate of the main NMOS is being clamped by another NMOS device. ___ | |___________ |___| | ___ |__________/\ __| | | | | \/ |___| _||<- | 5/5 | | ||____| | | || | | | ||____| | _/\ __| | 6u to drain | \/ | | | |_______ | | |__ | __| | 1/10 || | || 1/95*2 | ||___|__|| | <-|| ||-> | | | |_______|_____________| _|_ /// this structure tends to fail at 1000 volts and tends to pass 2000volts. present guess is the transister snap back happens at too high of an voltage and 2000 volts puts it into snap back sooner. Several experiments done and are in the process of being done. It is known the higher the gate voltage, the sooner the snap back as is shown below. ^ /|\ I | | c | u | r | // r | // e | / |_ Vg>0 n | |___\__ Vg=0 t |____________________/__/________\ Snap Back Breakdown Voltage / ___ _____ __/ Vg\_ ___ _|_ | \___/ | | | /// | | |___| | | | Source| Gate | Drain | Holes into Base __|__ __|___ __|__ from CB leakage __|_ _|__|______|__|_ _|_Base/Bulk voltage rises | N+ |---> | N+ |Electronsemitfrom emitter \________/--> <++\________/ Thresshold voltage lowered Substrate